14-bit, 125-MSPS ADS5500 evaluation

Introduction The ADS5500 is a high-speed, pipeline, CMOS ADC with 14-bit resolution and a 125-MSPS sampling rate. In March 2004 Texas Instruments (TI) introduced the device, which is the first ADC in the world market with such high sampling speed and high resolution. The ADS5500 is suitable for applications such as wireless communication, test and measurement instrumentation, control systems, medical imaging, and high-speed digitization. The ADS5500 consists of an input sample-and-hold stage; a 14-bit, pipeline ADC core; an internal voltage reference; a clocking circuit; digital error correction; a digital output driver; and a single 3.3-V voltage supply. The leading features and advantages of the ADS5500 are a wide signal input bandwidth of 750 MHz, a large dynamic differential input-signal range of 2.3 V peak-to-peak, a high signal-tonoise ratio (SNR) and spurious-free dynamic range (SFDR) at wide frequency range, a good SNR of up to 74 dBFS with low signal amplitude for receiver applications, and very low power dissipation (780 mW) at normal operation with a large load.1 For example, with a 125-MSPS sampling rate, a –1-dBFS signal amplitude, and an input frequency of 190 MHz with proper input configuration, the ADS5500 has a typical SNR of about 70 dB and an SFDR above 82 dB. With the same sampling frequency, the same input frequency, and a –15-dBFS input signal amplitude, the ADS5500 has an SNR of 74 dBFS and an SFDR of 83 dBFS. Since the ADS5500 has such high performance, it has a wide application; however, because of its high speed and high resolution, the device is sometimes challenging to evaluate. For this reason, this article introduces an ADS5500 evaluation system that includes the test equipment, system configuration, test circuit, basic high-speed ADC test concept, and test data.